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precision, dual-channel, jfet input, rail-to-rail instrumentation amplifier ad8224 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2007 analog devices, inc. all rights reserved. features two channels in a small 4 mm 4 mm lfcsp low input currents 10 pa maximum input bias current (b grade) 0.6 pa maximum input offset current (b grade) high cmrr 100 db cmrr (minimum), g = 10 (b grade) 90 db cmrr (minimum) to 10 khz, g = 10 (b grade) excellent ac specifications and low power 1.5 mhz bandwidth (g = 1) 14 nv/hz input noise (1 khz) slew rate: 2 v/s 750 a quiescent current per amplifier versatility rail-to-rail output input voltage range to below negative supply rail 4 kv esd protection 4.5 v to 36 v single supply 2.25 v to 18 v dual supply gain set with single resistor (g = 1 to 1000) applications medical instrumentation precision data acquisition transducer interfaces differential drives for high resolution input adcs remote sensors functional block diagram ad8224 1 2 3 4 12 11 10 9 5678 13141516 ?in1 r g1 r g1 +in1 ?in2 r g2 r g2 +in2 +v s ref1 ref2 ?v s +v s out1 out2 ?v s 06286-001 figure 1. table 1. in amps and difference amplifiers by category high perform low cost high voltage mil grade low power digital gain ad8220 1 ad8553 1 ad628 ad620 ad627 1 ad8231 1 ad8221 ad623 1 ad629 ad621 ad8250 ad8222 ad524 ad8251 ad526 ad8555 1 ad624 ad8556 1 ad8557 1 1 rail-to-rail output. general description the ad8224 is the first single-supply, jfet input instrumentation amplifier available in the space-saving 16-lead, 4 mm 4 mm lfcsp. it requires the same board area as a typical single instrumentation amplifier yet doubles the channel density and offers a lower cost per channel without compromising performance. designed to meet the needs of high performance, portable instrumentation, the ad8224 has a minimum common-mode rejection ratio (cmrr) of 86 db at dc and a minimum cmrr of 80 db at 10 khz for g = 1. maximum input bias current is 10 pa and typically remains below 300 pa over the entire industrial temperature range. despite the jfet inputs, the ad8224 typically has a noise corner of only 10 hz. with the proliferation of mixed-signal processing, the number of power supplies required in each system has grown. designed to alleviate this problem, the ad8224 can operate on a 18 v dual supply, as well as on a single +5 v supply. the devices rail-to-rail output stage maximizes dynamic range on the low voltage supplies common in portable applications. its ability to run on a single 5 v supply eliminates the need for higher voltage, dual supplies. the ad8224 draws 750 a of quiescent current per amplifier, making it ideal for battery powered devices. in addition, the ad8224 can be configured as a single-channel, differential output, instrumentation amplifier. differential outputs provide high noise immunity, which can be useful when the output signal must travel through a noisy environment, such as with remote sensors. the configuration can also be used to drive differential input adcs. for a single-channel version, use the ad8220 .
ad8224 rev. a | page 2 of 28 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 absolute maximum ratings ............................................................ 9 thermal resistance ...................................................................... 9 esd caution .................................................................................. 9 pin configuration and function descriptions ........................... 10 typical performance characteristics ........................................... 11 theory of operation ...................................................................... 20 gain selection ............................................................................. 20 reference terminal .................................................................... 21 layout .......................................................................................... 21 solder wash ................................................................................. 22 input bias current return path ............................................... 22 input protection ......................................................................... 22 rf interference ........................................................................... 23 common-mode input voltage range ..................................... 23 applications information .............................................................. 24 driving an adc ......................................................................... 24 differential output .................................................................... 24 driving a differential input adc ............................................ 25 driving cabling .......................................................................... 25 outline dimensions ....................................................................... 26 ordering guide .......................................................................... 26 revision history 4/07rev. 0 to rev. a changes to features, general description, and figure 1............ 1 changes to table 2............................................................................ 3 changes to table 3 and table 4....................................................... 5 changes to table 5............................................................................ 6 changes to table 6 and table 7....................................................... 8 changes to figure 2.......................................................................... 9 changes to figure 3........................................................................ 10 inserted figure 4, figure 5, and figure 6; renumbered sequentially ..................................................................................... 11 changes to figure 7........................................................................ 11 changes to figure 20 and figure 21............................................. 13 changes to figure 28...................................................................... 15 changes to theory of operation and figure 55......................... 20 changes to ordering guide .......................................................... 26 1/07revision 0: initial version
ad8224 rev. a | page 3 of 28 specifications v s + = +15 v, v s ? = ?15 v, v ref = 0 v, t a = 25c, g = 1, r l = 2 k 1 , unless otherwise noted. table 2 displays the specifications for an individual instrumentation amplifier configured for a single-ended output or dual instrumentation amplifiers configured for dif ferential outputs as shown in figure 62 . table 2. individual amplifier in single-ended configuration or dual amplifiers in differential output configuration 2 , v s = 15 v a grade b grade parameter test conditions min typ max min typ max unit common-mode rejection ratio (cmrr) cmrr dc to 60 hz with 1 k source imbalance v cm = 10 v g = 1 78 86 db g = 10 94 100 db g = 100 94 100 db g = 1000 94 100 db cmrr at 10 khz v cm = 10 v g = 1 74 80 db g = 10 84 90 db g = 100 84 90 db g = 1000 84 90 db noise rti noise = (e ni 2 + (e no /g) 2 ) voltage noise, 1 khz input voltage noise, e ni v in +, v in ? = 0 v 14 14 17 nv/hz output voltage noise, e no v in +, v in ? = 0 v 90 90 100 nv/hz rti, 0.1 hz to 10 hz g = 1 5 5 v p-p g = 1000 0.8 0.8 v p-p current noise f = 1 khz 1 1 fa/hz voltage offset rti v os = (v osi ) + (v oso /g) input offset, v osi 300 175 v average tc t = ?40c to +85c 10 5 v/c output offset, v oso 1200 800 v average tc t = ?40c to +85c 10 5 v/c offset rti vs. supply (psr) v s = 5 v to 15 v g = 1 86 86 db g = 10 96 100 db g = 100 96 100 db g = 1000 96 100 db input current (per channel) input bias current 25 10 pa over temperature 3 t = ?40c to +85c 300 300 pa input offset current 2 0.6 pa over temperature 3 t = ?40c to +85c 5 5 pa reference input r in 40 40 k i in v in +, v in ? = 0 v 70 70 a voltage range ?v s +v s ?v s +v s v gain to output 1 0.0001 1 0.0001 v/v
ad8224 rev. a | page 4 of 28 a grade b grade parameter test conditions min typ max min typ max unit gain g = 1 + (49.4 k/r g ) gain range 1 1000 1 1000 v/v gain error v out = 10 v g = 1 0.06 0.04 % g = 10 0.3 0.2 % g = 100 0.3 0.2 % g = 1000 0.3 0.2 % gain nonlinearity v out = ?10 v to +10 v g = 1 r l = 10 k 8 15 8 15 ppm g = 10 r l = 10 k 5 10 5 10 ppm g = 100 r l = 10 k 15 25 15 25 ppm g = 1000 r l = 10 k 100 150 100 150 ppm g = 1 r l = 2 k 15 20 15 20 ppm g = 10 r l = 2 k 12 20 12 20 ppm g = 100 r l = 2 k 35 50 35 50 ppm g=1000 r l = 2 k 180 250 180 250 ppm gain vs. temperature g = 1 3 10 2 5 ppm/c g > 10 ?50 ?50 ppm/c input impedance (pin to ground) 4 10 4 ||5 10 4 ||5 g||pf input operating voltage range 5 v s = 2.25 v to 18 v for dual supplies ?v s ? 0.1 +v s ? 2 ?v s ? 0.1 +v s ? 2 v over temperature t = ?40c to +85c ?v s ? 0.1 +v s ? 2.1 ?v s ? 0.1 +v s ? 2.1 v output output swing r l = 2 k ?14.25 +14.25 ?14.25 +14.25 v over temperature t = ?40c to + 85c ?14.3 +14.1 ?14.3 +14.1 v output swing r l = 10 k ?14.7 +14.7 ?14.7 +14.7 v over temperature t = ?40c to + 85c ?14.6 +14.6 ?14.6 +14.6 v short-circuit current 15 15 ma power supply (per amplifier) operating range 2.25 6 18 2.25 6 18 v quiescent current 750 800 750 800 a over temperature t = ?40c to +85c 850 900 850 900 a temperature range for specified performance ?40 +85 ?40 +85 c operational 7 ?40 +125 ?40 +125 c 1 when the output sinks more than 4 ma, use a 47 pf capacitor in parallel with the load to prevent ringing. otherwise, use a lar ger load, such as 10 k. 2 refers to the diff erential configuration shown in figure 62. 3 refer to figure 14 and figure 15 for the relati onship between input current and temperature. 4 differential and common-mode input impedance ca n be calculated from the pin impedance: z diff = 2(z pin ); z cm = z pin /2. 5 the ad8224 can operate up to a diode drop below the negative supply; however, the bias current increases sharply. the input vo ltage range reflects the maximum allowable voltage where the input bias current is within the specification. 6 at this supply voltage, ensure that the input common-mode vo ltage is within the input volt age range specification. 7 the ad8224 is characterized from ?40c to +125c. see the typical performance ch aracteristics section fo r expected operation i n this temperature range.
ad8224 rev. a | page 5 of 28 v s + = +15 v, v s ? = ?15 v, v ref = 0 v, t a = 25c, g = 1, r l = 2 k 1 , unless otherwise noted. table 3 displays the specifications for the dynamic performance of each individual instrumentation amplifier. table 3. dynamic performance of each individual amplifiersingle-ended output configuration, v s = 15 v a grade b grade parameter conditions min typ max min typ max unit dynamic response small signal bandwidth ?3 db g = 1 1500 1500 khz g = 10 800 800 khz g = 100 120 120 khz g =1000 14 14 khz settling time 0.01% v o = 10 v step g = 1 5 5 s g = 10 4.3 4.3 s g = 100 8.1 8.1 s g =1000 58 58 s settling time 0.001% v o = 10 v step g = 1 6 6 s g = 10 4.6 4.6 s g = 100 9.6 9.6 s g =1000 74 74 s slew rate g = 1 to 100 2 2 v/s 1 when the output sinks more than 4 ma, use a 47 pf capacitor in parallel with the load to prevent ringing. otherwise, use a lar ger load, such as 10 k. v s + = +15 v, v s ? = ?15 v, v ref = 0 v, t a = 25c, g = 1, r l = 2 k 1 , unless otherwise noted. table 4 displays the specifications for the dynamic performance of both amplifiers when used in the differential output configuration shown in figure 62 . table 4. dynamic performance of both ampl ifiersdifferential output configuration 2 , v s = 15 v a grade b grade parameter conditions min typ max min typ max unit dynamic response small signal bandwidth ?3 db g = 1 1500 1500 khz g = 10 800 800 khz g = 100 120 120 khz g =1000 14 14 khz settling time 0.01% v o = 10 v step g = 1 5 5 s g = 10 4.3 4.3 s g = 100 8.1 8.1 s g =1000 58 58 s settling time 0.001% v o = 10 v step g = 1 6 6 s g = 10 4.6 4.6 s g = 100 9.6 9.6 s g =1000 74 74 s slew rate g = 1 to 100 2 2 v/s 1 when the output sinks more than 4 ma, use a 47 pf capacitor in parallel with the load to prevent ringing. otherwise, use a lar ger load, such as 10 k. 2 refers to the diff erential configuration shown in figure 62.
ad8224 rev. a | page 6 of 28 v s + = 5 v, v s ? = 0 v, v ref = 2.5 v, t a = 25c, g = 1, r l = 2 k 1 , unless otherwise noted. table 5 displays the specifications for an individual instrumentation amplifier configured for a single-ended output or dual instrumentation amplifiers configured for dif ferential outputs as shown in figure 62 . table 5. individual amplifier in single-ended configuration or dual amplifiers in differential output configuration 2 , v s =+5 v a grade b grade parameter test conditions min typ max min typ max unit common-mode rejection ratio (cmrr) cmrr dc to 60 hz with 1 k source imbalance v cm = 0 to 2.5 v g = 1 78 86 db g = 10 94 100 db g = 100 94 100 db g = 1000 94 100 db cmrr at 10 khz g = 1 74 80 db g = 10 84 90 db g = 100 84 90 db g = 1000 84 90 db noise rti noise = (e ni 2 + (e no /g) 2 ) voltage noise, 1 khz v s = 2.5 v input voltage noise, e ni v in +, v in ? = 0 v, v ref = 0 v 14 14 17 nv/hz output voltage noise, e no v in +, v in ? = 0 v, v ref = 0 v 90 90 100 nv/hz rti, 0.1 hz to 10 hz g = 1 5 5 v p-p g = 1000 0.8 0.8 v p-p current noise f = 1 khz 1 1 fa/hz voltage offset rti v os = (v osi ) + (v oso /g) input offset, v osi 300 250 v average tc t = ?40c to +85c 10 5 v/c output offset, v oso 1200 800 v average tc t = ?40c to +85c 10 5 v/c offset rti vs. supply (psr) g = 1 86 86 db g = 10 96 100 db g = 100 96 100 db g = 1000 96 100 db input current (per channel) input bias current 25 10 pa over temperature 3 t = ?40c to +85c 300 300 pa input offset current 2 0.6 pa over temperature 3 t = ?40c to +85c 5 5 pa reference input r in 40 40 k i in v in +, v in ? = 0 v 70 70 a voltage range ?v s +v s ?v s +v s v gain to output 1 0.0001 1 0.0001 v/v
ad8224 rev. a | page 7 of 28 a grade b grade parameter test conditions min typ max min typ max unit gain g = 1 + (49.4 k/r g ) gain range 1 1000 1 1000 v/v gain error g = 1 v out = 0.3 v to 2.9 v 0.06 0.04 % g = 10 v out = 0.3 v to 3.8 v 0.3 0.2 % g = 100 v out = 0.3 v to 3.8 v 0.3 0.2 % g = 1000 v out = 0.3 v to 3.8 v 0.3 0.2 % nonlinearity v out = 0.3 v to 2.9 v for g = 1 v out = 0.3 v to 3.8 v for g > 1 g = 1 r l = 10 k 35 50 35 50 ppm g = 10 r l = 10 k 35 50 35 50 ppm g = 100 r l = 10 k 50 75 50 75 ppm g = 1000 r l = 10 k 90 115 90 115 ppm g = 1 r l = 2 k 35 50 35 50 ppm g = 10 r l = 2 k 35 50 35 50 ppm g = 100 r l = 2 k 50 75 50 75 ppm g = 1000 r l = 2 k 175 200 175 200 ppm gain vs. temperature g = 1 3 10 2 5 ppm/c g > 10 ?50 ?50 ppm/c input impedance (pin to ground) 4 10 4 ||6 10 4 ||6 g||pf input voltage range 5 ?0.1 +v s ? 2 ?0.1 +v s ? 2 v over temperature t = ?40c to +85c ?0.1 +v s ? 2.1 ?0.1 +v s ? 2.1 v output output swing r l = 2 k 0.25 4.75 0.25 4.75 v over temperature t = ?40c to +85c 0.3 4.70 0.3 4.70 v output swing r l = 10 k 0.15 4.85 0.15 4.85 v over temperature t = ?40c to +85c 0.2 4.80 0.2 4.80 v short-circuit current 15 15 ma power supply (per amplifier) operating range 4.5 36 4.5 36 v quiescent current 750 800 750 800 a over temperature t = ?40c to +85c 850 900 850 900 a temperature range for specified performance ?40 +85 ?40 +85 c operational 6 ?40 +125 ?40 +125 c 1 when the output sinks more than 4 ma, use a 47 pf capacitor in parallel with the load to prevent ringing. otherwise, use a lar ger load, such as 10 k. 2 refers to the diff erential configuration shown in figure 62. 3 refer to figure 14 and figure 15 for the relati onship between input current and temperature. 4 differential and common-mode impedance can be calculated from the pin impedance: z diff = 2(z pin ); z cm = z pin /2. 5 the ad8224 can operate up to a diode drop below the negative supply, but the bias current increases sh arply. the input voltage range reflects the maximum allowable voltage where the input bias current is within the specification. 6 the ad8224 is characterized from ?40c to +125c. see the typical performance ch aracteristics section fo r expected operation i n that temperature range.
ad8224 rev. a | page 8 of 28 v s + = 5 v, v s ? = 0 v, v ref = 2.5 v, t a = 25c, g = 1, r l = 2 k 1 , unless otherwise noted. table 6 displays the specifications for the dynamic performance of each individual instrumentation amplifier. table 6. dynamic performance of each individual amplifiersingle-ended output configuration, v s = +5 v a grade b grade parameter conditions min typ max min typ max unit dynamic response small signal bandwidth ?3 db g = 1 1500 1500 khz g = 10 800 800 khz g = 100 120 120 khz g =1000 14 14 khz settling time 0.01% g = 1 v o = 3 v step 2.5 2.5 s g = 10 v o = 4 v step 2.5 2.5 s g = 100 v o = 4 v step 7.5 7.5 s g =1000 v o = 4 v step 60 60 s settling time 0.001% g = 1 v o = 3 v step 3.5 3.5 s g = 10 v o = 4 v step 3.5 3.5 s g = 100 v o = 4 v step 8.5 8.5 s g =1000 v o = 4 v step 75 75 s slew rate g = 1 to 100 2 2 v/s 1 when the output sinks more than 4 ma, use a 47 pf capacitor in parallel with the load to prevent ringing. otherwise, use a lar ger load, such as 10 k. v s + = 5 v, v s ? = 0 v, v ref = 2.5 v, t a = 25c, g = 1, r l = 2 k 1 unless otherwise noted. table 7 displays the specifications for the dynamic performance of both amplifiers when used in the differential output configuration shown in figure 62 . table 7. dynamic performance of both ampl ifiersdifferential output configuration 2 , vs = +5 v a grade b grade parameter conditions min typ max min typ max unit dynamic response small signal bandwidth ?3 db g = 1 1500 1500 khz g = 10 800 800 khz g = 100 120 120 khz g =1000 14 14 khz settling time 0.01% g = 1 v o = 3 v step 2.5 2.5 s g = 10 v o = 4 v step 2.5 2.5 s g = 100 v o = 4 v step 7.5 7.5 s g =1000 v o = 4 v step 60 60 s settling time 0.001% g = 1 v o = 3 v step 3.5 3.5 s g = 10 v o = 4 v step 3.5 3.5 s g = 100 v o = 4 v step 8.5 8.5 s g =1000 v o = 4 v step 75 75 s slew rate g = 1 to 100 2 2 v/s 1 when the output sinks more than 4 ma, use a 47 pf capacitor in parallel with the load to prevent ringing. otherwise, use a lar ger load, such as 10 k. 2 refers to the diff erential configuration shown in figure 62.
ad8224 rev. a | page 9 of 28 absolute maximum ratings table 8. parameter rating supply voltage 18 v power dissipation see figure 2 output short-circuit current indefinite 1 input voltage (common mode) v s differential input voltage v s storage temperature range ?65c to +130c operating temperature range 2 ?40c to +125c lead temperature (soldering, 10 sec) 300c junction temperature 130c package glass transition temperature 130c esd (human body model) 4 kv esd (charge device model) 1 kv esd (machine model) 0.4 kv stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 1 assumes the load is referenced to midsupply. 2 temperature for specified performance is ?40c to +85c. for performance to 125c, see the typical performance characteristics section. thermal resistance table 9. thermal pad ja unit soldered to board 48 c/w not soldered to board 86 c/w the ja values in table 9 assume a 4-layer jedec standard board. if the thermal pad is soldered to the board, it is also assumed it is connected to a plane. jc at the exposed pad is 4.4c/w. maximum power dissipation the maximum safe power dissipation for the ad8224 is limited by the associated rise in junction temperature (t j ) on the die. at approximately 130 c, which is the glass transition temperature, the plastic changes its properties. even temporarily exceeding this temperature limit may change the stresses that the package exerts on the die, permanently shifting the parametric performance of the amplifiers. exceeding a temperature of 130c for an extended period can result in a loss of functionality. figure 2 shows the maximum safe power dissipation in the package vs. the ambient temperature for the lfcsp on a 4-layer jedec standard board. 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 ?60 ?40 ?20 0 20 40 60 80 100 120 140 06286-002 ambient temperature (c) maximum power dissipation (w) ja = 48c/w when thermal pad is soldered to board ja = 86c/w when thermal pad is not soldered to board figure 2. maximum power dissipation vs. ambient temperature esd caution
ad8224 rev. a | page 10 of 28 pin configuration and fu nction descriptions 12 11 10 9 ?in1 1 r g1 2 r g1 3 +v s 5 ref1 6 ref2 7 ?v s 8 +in1 4 16 15 14 13 pin 1 indicator top view ad8224 ?in2 r g2 r g2 +in2 +v s out1 out2 ?v s 06286-003 figure 3. pin configuration table 10. pin function descriptions pin number mnemonic description 1 ?in1 negative input instrumentation amplifier (in-amp) 1 2 r g1 gain resistor in-amp 1 3 r g1 gain resistor in-amp 1 4 +in1 positive input in-amp 1 5 +v s positive supply 6 ref1 reference adjust in-amp 1 7 ref2 reference adjust in-amp 2 8 ?v s negative supply 9 +in2 positive input in-amp 2 10 r g2 gain resistor in-amp 2 11 r g2 gain resistor in-amp 2 12 ?in2 negative input in-amp 2 13 ?v s negative supply 14 out2 output in-amp 2 15 out1 output in-amp 1 16 +v s positive supply
ad8224 rev. a | page 11 of 28 typical performance characteristics 25c, v s = 15 v, r l =10 k, unless otherwise noted. 06286-070 0 cmrr (v/v) number of units ?40 ?20 0 20 40 400 350 300 250 200 150 100 50 figure 4. typical distribution of cmrr (g = 1) 06286-071 0 v osi (v) number of units ?200 ?100 0 100 200 400 350 300 250 200 150 100 50 figure 5. typical distributi on of input offset voltage 06286-072 400 300 200 100 0 ?1200 ?900 ?600 ?300 0 300 600 900 1200 v oso (v) number of units figure 6. typical distribution of output offset voltage 1000 1 1 100k frequency (hz) voltage noise rti (nv/ hz) 10 100 1k 10k 10 100 gain = 100 bandwidth roll-off gain = 1 gain = 10 gain = 100/gain = 1000 gain = 1000 bandwidth roll-off 06286-009 figure 7. voltage spectral density vs. frequency x x xx xx xx xxx (x) xxx (x) 1s/div 5v/div 06286-010 figure 8. 0.1 hz to 10 hz rti voltage noise (g = 1) x x xx xx xx xxx (x) xxx (x) 1s/div 1v/div 06286-011 figure 9. 0.1 hz to 10 hz rti voltage noise (g = 1000)
ad8224 rev. a | page 12 of 28 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 0.1 1 10 100 1000 06286-012 time (s) delta v osi (v) figure 10. change in input offset voltage vs. warmup time 150 10 11 m frequency (hz) psrr (db) 10 100 1k 10k 100k 130 110 90 70 50 30 bandwidth limited gain = 1 gain = 10 gain = 100 gain = 1000 06286-013 frequency (hz) psrr (db) figure 11. positive psrr vs. frequency, rti 150 10 11 m 10 100 1k 10k 100k 130 110 90 70 50 30 gain = 1 gain = 10 gain = 100 gain = 1000 06286-014 figure 12. negative psrr vs. frequency, rti 0 6286-068 common-mode voltage (v) input bias current (pa) ?1 1 3 5 7 9 ?16 ?12 ?8 ?4 0 4 8 12 16 ?0.5 ?0.3 ?0.1 0.1 0.3 input offset current (pa) ?15.1v input bias current 15 input offset current 5 input bias current 5 ?5.1v input offset current 15 figure 13. input bias current and input offset current vs. common-mode voltage 10n 1n 100p 10p 1p 0.1p ?50 150 temperature (c) input bias current (a) i bias i os ?25 0 25 50 75 100 125 06286-016 10n 1n 100p 10p 1p 0.1p ?50 150 temperature (c) current (a) figure 14. input bias current and offset current vs. temperature, v s = 15 v, v ref = 0 v i bias i os ?25 0 25 50 75 100 125 06286-017 figure 15. input bias current and offset current vs. temperature, v s = 5 v, v ref = 2.5 v
ad8224 rev. a | page 13 of 28 40 60 80 100 120 140 160 10 100 1000 10000 100000 gain = 1000 gain = 100 gain = 10 gain = 1 06286-018 frequency (hz) cmrr (db) bandwidth limited figure 16. cmrr vs. frequency 40 60 80 100 120 140 160 1 10 100 1000 10000 100000 gain = 1000 gain = 100 gain = 1 gain = 10 06286-019 frequency (hz) cmrr (db) bandwidth limited figure 17. cmrr vs. frequency, 1 k source imbalance 0 1 3 5 2 4 6 7 ?50 ?30 ?10 10 30 50 70 90 110 130 06286-020 temperature (c) cmrr (v/v) figure 18. change in cmrr vs. temperature, g = 1 70 ?40 100 10m frequency (hz) gain (db) 1k 10k 100k 1m 60 50 40 30 20 10 0 ?10 ?20 ?30 gain = 1 gain = 10 gain = 100 gain = 1000 06286-021 figure 19. gain vs. frequency output voltage (v) xxx nonlinearity (10ppm/div) ?8 ?10 ?6?4?2 0 2 4 6 8 10 r load = 2k ? r load = 10k ? v s = 15v 06286-022 figure 20. gain nonlinearity, g = 1 output voltage (v) xxx nonlinearity (10ppm/div) ?8 ?10 ?6?4?2 0 2 4 6 8 10 r load = 2k ? r load = 10k ? v s = 15v 06286-023 figure 21. gain nonlinearity, g = 10
ad8224 rev. a | page 14 of 28 output voltage (v) xxx nonlinearity (20ppm/div) ?8 ?10 ?6 ?4 ?2 0 2 4 6 8 10 r load = 2k ? r load = 10k ? v s = 15v 06286-024 figure 22. gain nonlinearity, g = 100 output voltage (v) xxx nonlinearity (100ppm/div) ?8 ?10 ?6 ?4 ?2 0 2 4 6 8 10 r load = 2k ? r load = 10k ? v s = 15v 06286-025 figure 23. gain nonlinearity, g = 1000 18 ?18 ?16 16 output voltage (v) input common-mode voltage (v) 12 6 0 ?6 ?12 ?12?8?404812 ?15.3v +13v 15v supplies 5v supplies +14.9v, ?8.3v +14.9v, +5.5v +4.95v, ?3.3v +4.95v, +0.6v ?14.8v, +5.5v ?14.8v, ?8.3v ?4.8v, ?3.3v ?4.8v, +0.6v ?5.3v +3v 06286-026 figure 24. input common-mode voltage range vs. output voltage, g = 1, v ref = 0 v 012345 4 ?1 ?1 6 output voltage (v) input common-mode voltage (v) 3 2 1 0 ?0.3v +3v +4.9v, +0.5v +4.9v, +1.7v +5v single supply, v ref = +2.5v +0.1v, +0.5v +0.1v, +1.7v 06286-027 figure 25. input common-mode voltage range vs. output voltage, g = 1, v s = 5 v, v ref = 2.5 v 18 ?18 ?16 16 output voltage (v) input common-mode voltage (v) 12 6 0 ?6 ?12 ?12?8?404812 +13v ?15.3v 15v supplies +14.9v, ?9v +14.9v, +5.4v +4.9v, +0.5v +4.9v, ?4.1v ?4.9v, +0.4v ?4.9v, ?4.1v ?5.3v +3v ?14.8v, ?9v ?14.9v, +5.4v 5v supplies 06286-028 figure 26. input common-mode voltage range vs. output voltage, g = 100, v ref = 0 v 012345 4 ?1 ?1 6 output voltage (v) input common-mode voltage (v) 3 2 1 0 +3v ?0.3v +4.9v, +1.7v +4.9v, ?0.5v +0.1v, +1.7v +0.1v, ?0.5v +5v single supply, v ref = +2.5v 06286-029 figure 27. input common-mode voltage range vs. output voltage, g = 100, v s = 5 v, v ref = 2.5 v
ad8224 rev. a | page 15 of 28 v s + ?1 21 8 supply voltage (v) input voltage limit (v) ?1 ?2 +1 v s ? 4 6 8 10 12 14 16 ?40c +125c +25c +85c +25c ?40c notes 1. the ad8224 can operate up to a v be below the negative supply, but the bias current will increase sharply. +85c +125c 06286-030 figure 28. input voltage limit vs. supply voltage, g = 1, v ref =0 v v s + v s ? 21 8 dual supply voltage (v) output voltage swing (v) referred to supply voltages ?1 ?2 ?3 ?4 +4 +3 +2 +1 4 6 8 10121416 ?40c +25c +125c +85c ?40c +25c +85c +125c 06286-031 figure 29. output voltage swing vs. dual supply voltage, r load = 2 k, g = 10, v ref = 0 v v s + v s ? 21 8 06286-032 15 ?15 100 10k r load ( ? ) output voltage swing (v) dual supply voltage (v) output voltage swing (v) referred to supply voltages ?0.2 ?0.4 +0.4 +0.2 4 6 8 10 12 14 16 +85c +125c +25c ?40c ?40c +25c +85c +125c figure 30. output voltage swing vs. dual supply voltage, r load = 10 k, g = 10, v ref = 0 v 1k +125c +85c +25c ?40c 10 5 0 ?5 ?10 +125c +85c +25c ?40c 06286-033 5 0 100 10k r load ( ? ) output voltage swing (v) figure 31. output voltage swing vs. load resistance, v s = 15 v, v ref = 0 v 1k 4 3 2 1 ?40c ?40c +125c +125c +85c +25c +25c +85c 06286-034 figure 32. output voltage swing vs. load resistance, v s = 5 v, v ref = 2.5 v v s + v s ? 01 6 i out (ma) output voltage swing (v) referred to supply voltages ?40c ?1 ?2 ?3 ?4 +4 +3 +2 +1 +125c +85c +25c +25c +85c +125c ?40c 2 4 6 8 101214 06286-035 figure 33. output voltage swing vs. output current, v s = 15 v, v ref = 0 v
ad8224 rev. a | page 16 of 28 v s + v s ? 01 6 35 0 100 10m frequency (hz) output voltage swing (v p-p) i out (ma) output voltage swing (v) referred to supply voltages ?1 ?2 +2 +1 2 4 6 8 101214 ?40c +125c +85c +25c +125c +25c +85c gain = 10, 100, 1000 30 25 20 15 10 5 gain = 1 1k 10k 100k 1m 06286-039 06286-036 figure 34. output voltage swing vs. output current, v s = 5 v, v ref = 2.5 v xx xx xx xx xxx (x) xxx (x) 5s/div 20mv/div 100pf 47pf no load 06286-037 figure 35. small signal pulse response for various capacitive loads, v s = 15 v, v ref = 0 v xx xx xx xx xxx (x) xxx (x) 5s/div 20mv/div 100pf 47pf no load 06286-038 figure 36. small signal pulse response for various capacitive loads, v s = 5 v, v ref = 2.5 v figure 37. output voltage swing vs. large signal frequency response x x xx xx xx xxx (x) xxx (x) 20s/div 5s to 0.01% 6s to 0.001% 5v/div 0.002%/div 06286-040 figure 38. large signal pulse response and settle time, g = 1, r load = 10 k, v s = 15 v, v ref = 0 v x x xx xx xx xxx (x) xxx (x) 20s/div 5v/div 4.3 s to 0.01% 4.6 s to 0.001% 0.002%/div 06286-041 figure 39. large signal pulse response and settle time, g = 10, r load = 10 k, v s = 15 v, v ref = 0 v
ad8224 rev. a | page 17 of 28 xx xx xx xx xxx (x) xxx (x) 20s/div 8.1 s to 0.01% 9.6 s to 0.001% 0.002%/div 5v/div 06286-042 figure 40. large signal pulse response and settle time, g = 100, r load = 10 k, v s = 15 v, v ref = 0 v xx xx xx xx xxx (x) xxx (x) 200s/div 58 s to 0.01% 74 s to 0.001% 0.002%/div 5v/div 06286-043 figure 41. large signal pulse response and settle time, g = 1000, r load = 10 k, v s = 15 v, v ref = 0 v xxx xxx 4s/div 20mv/div 06286-044 figure 42. small signal pulse response, g = 1, r load = 2 k, c load = 100 pf, v s = 15 v, v ref = 0 v xxx xxx 4s/div 20mv/div 06286-045 figure 43. small signal pulse response, g = 10, r load = 2 k, c load = 100 pf, v s = 15 v, v ref = 0 v xxx xxx 4s/div 20mv/div 06286-046 figure 44. small signal pulse response, g = 100, r load = 2 k, c load = 100 pf, v s = 15 v, v ref = 0 v xxx xxx 20mv/div 40s/div 06286-047 figure 45. small signal pulse response, g = 1000, r load = 2 k, c load = 100 pf, v s = 15 v, v ref = 0 v
ad8224 rev. a | page 18 of 28 xxx xxx 4s/div 20mv/div 06286-048 figure 46. small signal pulse response, g = 1, r load = 2 k, c load = 100 pf, v s = 5 v, v ref = 2.5 v xxx xxx 4s/div 20mv/div 06286-049 figure 47. small signal pulse response, g = 10, r load = 2 k, c load = 100 pf, v s = 5 v, v ref = 2.5 v xxx xxx 4s/div 20mv/div 06286-050 figure 48. small signal pulse response, g = 100, r load = 2 k, c load = 100 pf, v s = 5 v, v ref = 2.5 v xxx xxx 40s/div 20mv/div 06286-051 figure 49. small signal pulse response, g = 1000, r load = 2 k, c load = 100 pf, v s = 5 v, v ref = 2.5 v 15 0 02 output voltage step size (v) settling time (s) 0 10 5 51 01 5 settled to 0.01% settled to 0.001% 06286-052 figure 50. settling time vs. output voltage step size, (g = 1) 15 v, v ref = 0 v 100 1 1 1000 gain (v/v) settling time (s) 10 100 10 settled to 0.01% settled to 0.001% 06286-053 figure 51. settling time vs. gain for a 10 v step, v s = 15 v, v ref = 0 v
ad8224 rev. a | page 19 of 28 1 10k 1k 100 10 100k 1m frequency (hz) 06286-056 100 90 80 70 60 50 40 30 20 10 0 cmr out (db) limited by measurement system cmr out = 20 log v diff_out v cm_out 06286-069 frequency (hz) channel separation (db) 40 60 80 100 120 140 160 180 1 10 100 1k 10k 100k 1m thermal crosstalk varies with load gain = 1000 gain = 1 source v out = 20v p-p source v out smaller to avoid slew rate limit figure 54. differential output configuration: common-mode output (cmr out ) vs. frequency figure 52. channel separation vs. frequency, r load = 2 k, source channel at g = 1 ?40 ?20 0 20 40 60 06286-055 frequency (hz) gain (db) 10k 1k 100 100k 1m 10m gain = 1 gain = 10 gain = 100 gain = 1000 figure 53. differential output configuration: gain vs. frequency
ad8224 rev. a | page 20 of 28 theory of operation q2 q1 node a node b node c node d vb c1 c2 a1 a2 ?v s +v s ?v s j1 + in v pinch +v s ?v s j2 ?in v pinch + v s ?v s r g + v s + v s + v s ?v s 20k ? 20k ? 20k ? 20k ? +v s ?v s +v s ?v s ref output a3 node e node f i i r2 24.7k ? r1 24.7k ? 06286-057 figure 55. simplified schematic the ad8224 is a jfet input, monolithic instrumentation amplifier based on the classic three op amp topology (see figure 55 ). input transistor j1 and input transistor j2 are biased at a fixed current so that any input signal forces the output voltages of a1 and a2 to change accordingly. the input si gnal creates a current through r g that flows in r1 and r2 such that the outputs of a1 and a2 provide the correct, gained signal. topologically, j1, a1, and r1 and j2, a2, and r2 can be viewed as precision current feedback amplifiers with a gain bandwidth of 1.5 mhz. the common-mode voltage and amplified differential signal from a1 and a2 are applied to a difference amplifier that rejects the common-mode voltage but amplifies the differential signal. the difference amplifier employs 20 k laser trimmed resistors that result in an in-amp with a gain error of less than 0.04%. new trim techniques were developed to ensure that the cmrr exceeds 86 db (g = 1). using jfet transistors, the ad8224 offers an extremely high input impedance, extremely low bias currents of 10 pa maximum, low offset current of 0.6 pa maximum, and no input bias current noise. in addition, input offset is less than 175 v and drift is less than 5 v/c. ease of use and robustness were considered. a common problem for instrumentation amplifiers is that at high gains, when the input is overdriven, an excessive milliampere input bias current can result, and the output can undergo phase reversal. overdriving the input at high gains refers to when the input signal is within the supply voltages but the amplifier cannot output the gained signal. for example, at a gain of 100, driving the amplifier with 10 v on 15 v constitutes overdriving the inputs because the amplifier cannot output 100 v. the ad8224 has none of these problems; its input bias current is limited to less than 10 a, and the output does not phase reverse under overdrive fault conditions. the ad8224 has extremely low lo ad induced nonlinearity. all amplifiers that comprise the ad8224 have rail-to-rail output capability for enhanced dynamic range. the input of the ad8224 can amplify signals with wide common-mode voltages even slightly lower than the negative supply rail. the ad8224 operates over a wide supply voltage range. it can operate from either a single +4.5 v to +36 v supply or a dual 2.25 v to 18 v. the transfer function of the ad8224 is g r g k 49.4 1 += users can easily and accurately set the gain using a single, standard resistor. because the input amplifiers employ a current feedback architecture, the ad8224 gain bandwidth product increases with gain, resulting in a system that does not experience as much bandwidth loss as voltage feedback architectures at higher gains. gain selection placing a resistor across the r g terminals sets the gain of the ad8224. this is calculated by referring to tabl e 11 or by using the following gain equation 1 k 49.4 ? = g r g
ad8224 rev. a | page 21 of 28 table 11. gains achieved using 1% resistors 1% standard table value of r g () calculated gain 49.9 k 1.990 12.4 k 4.984 5.49 k 9.998 2.61 k 19.93 1.00 k 50.40 499 100.0 249 199.4 100 495.0 49.9 991.0 the ad8224 defaults to g = 1 when no gain resistor is used. the tolerance and gain drift of the r g resistor should be added to the ad8224 specifications to determine the total gain accuracy of the system. when the gain resistor is not used, gain error and gain drift are kept to a minimum. reference terminal the output voltage of the ad8224 is developed with respect to the potential on the reference terminal. this is useful when the output signal needs to be offset to a precise midsupply level. for example, a voltage source can be tied to the ref1 pin or the ref2 pin to level-shift the output so that the ad8224 can drive a single-supply adc. pin refx is protected with esd diodes and should not exceed either +v s or ?v s by more than 0.5 v. for best performance, source impedance to the ref terminal should be kept below 1 . as shown in figure 55 , the reference terminal, ref, is at one end of a 20 k resistor. additional impedance at the ref terminal adds to this 20 k resistor and results in amplification of the signal connected to the positive input. the amplification from the additional r ref can be computed by ( ) ref ref r r + + k 40 k 202 only the positive signal path is amplified; the negative path is unaffected. this uneven amplification degrades the cmrr of the amplifier. incorrect ad8224 v ref correct ad8224 op2177 + ? v ref correct ad8224 ad8224 + ? v ref 06286-058 figure 56. driving the reference pin layout the ad8224 is a high precision device. to ensure optimum performance at the pcb level, care must be taken in the design of the board layout. the ad8224 pinout is arranged in a logical manner to aid in this task. package considerations the ad8224 is available in a 16-lead, 4 mm 4 mm lfcsp. blindly copying the footprint from another 4 mm 4 mm lfcsp part is not recommended because it may not have the same thermal pad size and leads. refer to the outline dimensions section to verify that the pcb symbol has the correct dimensions. space between the leads and thermal pad should be kept as wide as possible for the best bias current performance. to maintain the ad8224 ultralow bias current performance, the thermal pad area can be reduced to extend the gap between the leads and the pad. thermal pad the ad8224 4 mm 4 mm lfcsp comes with a thermal pad. this pad is connected internally to +v s . the pad can either be left unconnected or connected to the positive supply rail. to preserve maximum pin compatibility with other dual instrumentation amplifiers, such as the ad8222 , leave the pad unconnected. this can be done by not soldering the paddle at all or by soldering the part to a landing that is a not connected to any other net. for high vibration applications, a landing is recommended. because the ad8224 dissipates little power, heat dissipation is rarely an issue. if improved heat dissipation is desired (for example, when driving heavy loads), connect the thermal pad to the positive supply rail. for the best heat dissipation performance, the positive supply rail should be a plane in the board. see the thermal resistance section for more information. common-mode rejection over frequency the ad8224 has a higher cmrr over frequency than typical in-amps, which gives it greater immunity to disturbances, such as line noise and its associated harmonics. a well-implemented layout is required to maintain this high performance. input source impedances should be matched closely. source resistance should be placed close to the inputs so that it interacts with as little parasitic capacitance as possible. parasitics at the r gx pins can also affect cmrr over frequency. the pcb should be laid out so that the parasitic capacitances at each pin match. traces from the gain setting resistor to the r gx pins should be kept short to minimize parasitic inductance. reference errors introduced at the reference terminal feed directly to the output. take care to tie the refx pins to the appropriate local ground.
ad8224 rev. a | page 22 of 28 power supplies a stable dc voltage should be used to power the instrumentation amplifier. noise on the supply pins can adversely affect performance. the ad8224 has two positive supply pins (pin 5 and pin 16) and two negative supply pins (pin 8 and pin 13). while the part functions with only one pin from each supply pair connected, both pins should be connected for specified performance and optimum reliability. the ad8224 should be decoupled with 0.1 f bypass capacitors, one for each supply. place the positive supply decoupling capacitor near pin 16, and the negative supply decoupling capacitor near pin 8. each supply should also be decoupled with a 10 f tantalum capacitor. the tantalum capacitor can be placed further away from the ad8224 and can generally be shared by other precision integrated circuits. figure 57 shows an example layout. ad8224 1 2 3 4 12 11 9 5678 1314 15 16 0.1f 0.1f r g r g 10 06286-059 figure 57. ex ample layout solder wash the solder process can leave flux and other contaminants on the board. when these contaminants are between the ad8224 leads and thermal pad, they can create leakage paths that are larger than the ad8224 bias currents. a th orough washing process removes these contaminants and restores the devices excellent bias current performance. input bias current return path the input bias current of the ad8224 must have a return path to common. when the source, such as a transformer, cannot provide a return current path, one should be created, as shown in figure 58 . input protection all terminals of the ad8224 are protected against esd. esd protection is guaranteed to 4 kv (human body model). in addition, the input structure allows for dc overload conditions a diode drop above the positive supply and a diode drop below the negative supply. voltages beyond a diode drop of the supplies cause the esd diodes to conduct and enable current to flow through the diode. therefore, an external resistor should be used in series with each of the inputs to limit current for voltages above +vs. in either scenario, the ad8224 safely handles a continuous 6 ma current at room temperature. for applications where the ad8224 encounters extreme overload voltages, as in cardiac defibrillators, external series resistors and low leakage diode clamps, such as bav199ls, fjh1100s, or sp720s, should be used. transformer +v s ref ?v s ad8224 incorrect transformer +v s ref ?v s ad8224 correct capacitively coupled +v s ref c c ?v s ad8224 capacitively coupled +v s ref c r r c ?v s ad8224 1 f high-pass = 2 rc 0 6286-060 figure 58. creating an i bias path
ad8224 rev. a | page 23 of 28 rf interference mismatched c c capacitors result in mismatched low-pass filters. the imbalance causes the ad8224 to treat what would have been a common-mode signal as a differential signal. to reduce the effect of mismatched external c c capacitors, select a value of c d greater than 10 times c c . this sets the differential filter frequency lower than the common-mode frequency. rf rectification is often a problem in applications where there are large rf signals. the problem appears as a small dc offset voltage. the ad8224 by its nature has a 5 pf gate capacitance (c g ) at its inputs. matched series resistors form a natural low-pass filter that reduces rectification at high frequency (see figure 59 ). r r ad8224 +15 v +in ?in 0.1f 10f 10f 0.1f ref v out ?15v c d c c c c 10nf 1nf 1nf 4.02k ? 4.02k ? 06286-062 + + the relationship between external, matched series resistors and the internal gate capacitance is expressed as g diff rc filterfreq = 2 1 g cm rc filterfreq = 2 1 ad8224 v out c g c g ?v s ref ?v s r r +in ?in +15 v ?15v 0.1f 10f 0.1f 10f 06286-061 + + figure 60. rfi suppression common-mode input voltage range the 3-op amp architecture of the ad8224 applies gain and then removes the common-mode voltage. therefore, internal nodes in the ad8224 experience a combination of both the gained signal and the common-mode signal. this combined signal can be limited by the voltage supplies even when the individual input and output signals are not. figure 24 through figure 27 show the allowable common-mode input voltage ranges for various output voltages, supply voltages, and gains. figure 59. rfi filtering without external capacitors to eliminate high frequency common-mode signals while using smaller source resistors, a low-pass rc network can be placed at the input of the instrumentation amplifier (see figure 60 ). the filter limits the input signal bandwidth according to the following relationship: ) 2(2 1 g cd diff cccr filterfreq + + = )(2 1 g c cm ccr filterfreq + =
ad8224 rev. a | page 24 of 28 applications information driving an adc an instrumentation amplifier is often used in front of an adc to provide cmrr and additional conditioning such as a voltage level shift and gain (see figure 61 ). in this example, a 2.7 nf capacitor and a 500 resistor create an antialiasing filter for the ad7685 . the 2.7 nf capacitor also serves to store and deliver the necessary charge to the switched capacitor input of the adc. the 500 series resistor reduces the burden of the 2.7 nf load from the amplifier. however, large source impedance in front of the adc can degrade the total harmonic distortion (thd). for applications where thd performance is critical, the series resistor needs to be small. at worst, a small series resistor can load the ad8224, potentially causing the output to overshoot or ring. in such cases, a buffer amplifier, such as the ad8615 should be used after the ad8224 to drive the adc. ad8224 ad7685 4.7f adr435 +5v 2.7nf ref 500 ? 1.07k ? +2.5v +in ?in 50mv +5v 0.1f 10f 06286-063 + figure 61. driving an adc in a low frequency application differential output the differential configuration of the ad8224 has the same excellent dc precision specifications as the single-ended output configuration and is recommended for applications in the frequency range of dc to 1 mhz. the circuit configuration, outlined in table 4 and table 7 , refers to the configuration shown in figure 62 only. the circuit includes an rc filter that maintains the stability of the loop. the transfer function for the differential output is v diff_out = v +out ? v ?out = ( v +in ? v ?in ) g where: g r g k 49.4 1 += +in ?in + ? + ? ad8224 ad8224 +out 33pf ?out +in2 ref2 20k? r g 06286-064 figure 62. differential circuit schematic setting the common-mode voltage the output common-mode voltage is set by the average of +in2 and ref2. the transfer function is v cm_out = ( v +out + v ?out )/2 = ( v +in2 + v ref2 )/2 +in2 and ref2 have different properties that allow the reference voltage to be easily set for a wide variety of applications. +in2 has high impedance but cannot swing to the positive supply rail. ref2 must be driven with a low impedance but can go 300 mv beyond the supply rails. a common application sets the common-mode output voltage to the midscale of a differential adc. in this case, the adc reference voltage is sent to the +in2 terminal, and ground is connected to the ref2 terminal. this produces a common- mode output voltage of half the adc reference voltage. 2-channel differential output using a dual op amp another differential output topology is shown in figure 63 . instead of a second in-amp, ? of a dual op2177 op amp creates the inverted output. because the op2177 comes in an msop, this configuration allows the creation of a dual-channel, precision differential output in-amp with little board area. errors from the op amp are common to both outputs and are, thus, common mode. errors from mismatched resistors also create a common-mode dc offset. because these errors are common mode, they are likely to be rejected by the next device in the signal chain. +in ?in ref ad8224 v ref 4.99k ? + ? op2177 +out ?out 4.99k ? 06286-065 figure 63. differential output using op amp
ad8224 rev. a | page 25 of 28 ad8224 (diff out) 100pf npo 5% 100pf npo 5% 1000pf ?in +in 0.1f 10f 0.1f 10f ?12v +12 v 1k ? 1k ? + + in+ vdd gnd ref 10f x5r ad7688 in? 0.1f +5v adr435 gnd v in v out 0.1f +12v 0.1f +5v ref +in2 ref2 +5v ref +out ?out 806? 2.7nf 2.7nf 806? 06286-066 figure 64. driving a differential adc driving a differential input adc the ad8224 can be configured in differential output mode to drive a differential adc. figure 64 illustrates several of the concepts. first antialiasing filter the 1 k resistor, 1000 pf capacitor, and 100 pf capacitors in front of the in-amp form a 76 khz filter. this is the first of two antialiasing filters in the circuit and helps to reduce the noise of the system. the 100 pf capacitors protect against common- mode rfi signals. note that they are 5% cog/npo types. these capacitors match well over time and temperature, which keeps the cmrr of the system high over frequency. second antialiasing filter an 806 resistor and a 2.7 nf capacitor are located between each ad8224 output and adc input. these components create a 73 khz low-pass filter for another stage of antialiasing protection. these four elements also isolate the adc from loading the ad8224. the 806 resistor shields the ad8224 from the switched capacitor input of the adc, which looks like a time- varying load. the 2.7 nf capacitor provides a charge to the switched capacitor front end of the adc. if the application requires a lower frequency antialiasing filter, increase the value of the capacitor rather than the resistor. the 806 resistors can also protect an adc from overvoltages. because the ad8224 runs on wider supply voltages than a typical adc, there is a possibility of overdriving the adc. this is not an issue with a pulsar? converter, such as the ad7688 . its input can handle a 130 ma overdrive, which is much higher than the short-circuit limit of the ad8224. however, other converters have less robust inputs and may need the added protection. reference the adr435 supplies a reference voltage to both the adc and the ad8224. because ref2 on the ad8224 is grounded, the common-mode output voltage is precisely half the reference voltage, exactly where it needs to be for the adc. driving cabling all cables have a certain capacitance per unit length, which varies widely with cable type. the capacitive load from the cable may cause peaking in the ad8224 output response. to reduce peaking, use a resistor between the ad8224 and the cable. because cable capacitance and desired output response vary widely, this resistor is best determined empirically. a good starting point is 50 . the ad8224 operates at a low enough frequency that transmission line effects are rarely an issue; therefore, the resistor need not match the characteristic impedance of the cable. ad8224 (diff out) ad8224 (single out) 06286-067 figure 65. driving a cable
ad8224 rev. a | page 26 of 28 outline dimensions compliant to jedec standards mo-220-vggc. 1 0.65 bsc 0.60 max p i n 1 i n d i c a t o r 1.95 bcs 0.50 0.40 0.30 0.25 min 3.75 bsc sq top view 12 max 0.80 max 0.65 typ seating plane pin 1 indicator coplanarity 0.08 1.00 0.85 0.80 0.30 0.23 0.18 0.05 max 0.02 nom 0.20 ref 4.00 bsc sq 2.65 2.50 sq 2.35 16 5 13 8 9 12 4 exposed pa d bottom view 031006-a figure 66. 16-lead lead frame chip scale package [lfcsp_vq] 4 mm 4 mm body, very thin quad (cp-16-13) dimensions are shown in millimeters ordering guide model temperature range product description package option ad8224acpz-r7 1 ?40c to +85c 16-lead lfcsp_vq cp-16-13 ad8224acpz-rl 1 ?40c to +85c 16-lead lfcsp_vq cp-16-13 ad8224acpz-wp 1 ?40c to +85c 16-lead lfcsp_vq cp-16-13 AD8224BCPZ-R7 1 ?40c to +85c 16-lead lfcsp_vq cp-16-13 ad8224bcpz-rl 1 ?40c to +85c 16-lead lfcsp_vq cp-16-13 ad8224bcpz-wp 1 ?40c to +85c 16-lead lfcsp_vq cp-16-13 ad8224-evalz 1 evaluation board 1 z = rohs compliant part.
ad8224 rev. a | page 27 of 28 notes
ad8224 rev. a | page 28 of 28 notes ?2007 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d06286-0-4/07(a)

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